Memory safety

A Sixty-Year-Old Problem # Memory safety bugs have been the single largest class of security vulnerabilities since the Morris Worm in 1988. Despite decades of research, tooling improvements, and coding standards, they remain the dominant cause of exploitable defects in systems software.

The Defense-in-Depth Approach # Because no single technique eliminates all memory safety risks, modern systems employ multiple layers of defense. This page surveys the major software-based approaches — their strengths, overheads, and fundamental limitations.

Why Hardware? # Software-based memory safety defenses — sanitizers, ASLR, stack canaries, CFI — operate at the same privilege level as the code they protect. A sufficiently powerful attacker can disable or bypass them. Hardware-assisted approaches enforce safety properties below the software layer, in silicon that cannot be reprogrammed by an exploit.

How MTE Works # Arm’s Memory Tagging Extension (MTE), introduced in ARMv9, is the most widely deployed hardware memory safety technology as of 2025. It provides probabilistic protection against spatial and temporal memory safety violations at low runtime cost.

What Is CHERI? # CHERI (Capability Hardware Enhanced RISC Instructions) is a set of ISA extensions, developed since 2010 by the University of Cambridge and SRI International, that replace raw machine pointers with capabilities — hardware-enforced tokens of authority that carry their own bounds, permissions, and validity. Unlike other hardware memory safety approaches, CHERI provides: Deterministic protection (not probabilistic) Spatial and temporal safety in a single mechanism Fine-grained compartmentalization within a single process Secret-free defense (nothing to leak)

AI Makes the Problem Worse # AI systems don’t just inherit the memory safety risks of their underlying software — they amplify them. The AI stack introduces new attack surfaces, higher-stakes failure modes, and unique operational constraints that make traditional defenses insufficient.